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TDK SEMICONDUCTOR CORP.
5503 DCR Direct Conversion Receiver Advanced Information
February 2001
DESCRIPTION
The 5503 is a low cost, high performance direct conversion receiver (DCR) specifically designed for digital wireless applications. The DCR architecture provides a receiver design with fewer external components than the conventional dual conversion approach. The 5503 is designed to operate over an input frequency range of 950 to 1450 MHz. The device accepts an input signal in this frequency range and down converts directly to baseband. The local oscillator signal is generated by a completely integrated phase lock loop that is fully programmable through a standard serial port interface.
FEATURES
* Wideband I/Q demodulator
- RF input 950 to 1450 MHz - External lowpass filter - Integrated post-filter baseband drivers * Integrated VCO and frequency synthesizer * AGC Amplifier
APPLICATIONS
* Digital Satellite
* VSAT Receivers
BLOCK DIAGRAM
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5503 DCR Direct Conversion Receiver
FUNCTIONAL DESCRIPTION
AGC Amplifier The 5503 RF input can be driven differentially or single ended. The RFp and RFn inputs are selfbiasing and are designed to be driven from a 50 Ohm source. For single-ended operation, the RFn pin should be AC coupled to analog ground. A gain control input, AGC, provides a 22 dB gain variation with 0V providing minimum gain and 4V providing maximum gain. I/Q Mixer The AGC amplifier drives the RF port of two identical double balanced mixers. The LO ports of these mixers are driven from an on-chip quadrature network. Low Pass Filtering and Buffering Following each mixer is a buffer amplifier for driving an external passive low-pass filter. An external series resistor connected to the IO1 or QO1 output is used to provide the source match for the filter. A second high impedance buffer amplifier is provided (IIN or QIN) for additional gain and isolation after the filter. The figure below shows a typical filter designed for 20 Megasymbol per second operation:

Note: A separate resonator circuit is required for each oscillator PLL Synthesizer The synthesizer derives its reference from a source which can be either an externally derived clock or an external crystal coupled to the internal oscillator. This source drives a programmable reference divider with 15 preset divide ratios from 2 to 320. This output provides the PLL reference by driving one input of a phase/frequency detector. The VCO output drives a divider chain incorporating a selectable divide by two prescaler followed by a variable modulus prescaler and divider. The divider is programmed by a 17-bit control word. This divider chain output drives the other input of the phase/frequency detector. Loop Filter The phase/frequency detector provides two output pairs, FILN/EON and FILP/EOP. The FILN/EON outputs are used when the VCO has a positive gain characteristic (increasing voltage yields increasing frequency). The FILP/EOP outputs are used for a negative VCO gain characteristic. Below is shown a typical loop filter:
Dual VCO The 5503 uses two VCOs to cover the entire specified tuning range. Both VCOs use nearly identical architecture with the only difference being slight design modifications to optimize the range of operation. The lower range VCO requires an external resonator that supports a tuning range of 950 to 1150 MHz. The higher range VCO requires a similar resonator with inductor values designed to support the range of 1100 to 1475 MHz. A typical lumped-element resonator circuit incorporating varactor tuning is shown in the following figure:
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5503 DCR Direct Conversion Receiver
DCR Application Drawing
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5503 DCR Direct Conversion Receiver
PIN DESCRIPTIONS
ANALOG PINS NAME RFP, RFN TYPE I DESCRIPTION RF inputs: balanced differential inputs to the receiver. The input signals placed on this line are amplified with a variable gain amplifier before being passed to the I/Q demodulator. Automatic gain control input. A voltage from 0 to 4 volts on this pin varies the input amplifier gain from minimum to maximum. The gain increase is 22 dB typical External loop filter interface. Eop drives the base of an external common emitter transistor. Filp is the feedback input from the loop filter capacitor. This output is used for a negative VCO gain characteristic. External loop filter interface. Eon drives the base of an external common emitter transistor. Filn is the feedback input from the loop filter capacitor. This output is used for a positive VCO gain characteristic. Reference crystal input. An external crystal connected between these pins establishes the reference frequency for the PLL synthesizer. The crystal frequency must be 8 MHz and have an ESR of less than 100 Ohms. Following this oscillator is a programmable divider which establishes the synthesizer step size. Baseband outputs. These typically drive an A/D converter prior to digital demodulation and processing. I and Q channel outputs to external low pass filter. An external series resistor is connected between this output and the filter to provide the source match. I and Q channel inputs from external low pass filter. These are high impedance inputs ( >1000). The low pass filter must be designed for a low input and high output impedance. External reference resistor. This resistor is connected to ground and must be 7.68k 1% . It is used as a reference for internal bias currents. High range VCO resonator inputs Low range VCO resonator inputs
AGC Eop, Filp
I I/O
Eon, Filn
I/O
XTLP, XTLN
I
IO2, QO2 IO1, QO1 IIN, QIN
O O I
Rxt RSHP, RSHN RSLP, RSLN DIGITAL PINS Din Dclk
I I I
I/O I
I2C data. This signal is connected to the I2C internal block. An external resistor (typically 2.2 k) is connected between Din and Vcc for proper operation I2C clock Input: Dclk should nominally be a square wave with a maximum frequency of 400kHz. SCL is generated by the system I2C master
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5503 DCR Direct Conversion Receiver
POWER PINS VPA1, VPA2, VPA3a, VPA3b, VPA4, VPA5a, VPA5b, VPA6 VPD1, VPD2 VNA1, VNA2, VNA3a, VNA3b, VNA4, VNA6, VNA7 VND1 VNS I Analog Vcc pins
I I
Digital Vcc pin. Analog ground pins.
I I
Digital ground pin. Substrate ground pin.
MICROCONTROLLER SERIAL INTERFACE I C REGISTERS: WRITE MODE
2
S
address
0 A reg0
A
reg1
A reg2
A
reg3
5503 address 1 1 0 0 0 0 1
S : start bit A : acknowledge bit P : stop bit TABLE 1: MICROCONTROLLER INTERFACE REGISTER REGISTER 0 1 2 3 7(MSB) 0 2
7
6 2
14 6 16
5 2
13 5 15
4 2 2
12 4
3 2
11 3
2 2
10 2
1 2
9 1
0 (LSB) 2 2
8 0
2 2
2 2
2
2
2
1 C1
PE test0
R3 test2
R2 vco1
R1 vco0
R0 x
C0
test1
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5503 DCR Direct Conversion Receiver
DESCRIPTION OF INTERNAL REGISTERS Register 0 Register 1 Register 2 VCO divide ratio, bits 14 thru 8, msb always set to 0 VCO divide ratio, bits 7 thru 0 msb Not Used. Always set to 1 VCO divide ratio, bits 16 and 15 PE, Prescaler enable. PE=1 enables divide by two prescaler R3,R2,R1,R0 Reference division ratio, as shown in following table: R3 R2 R1 R0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Register 3 C1, C0 Reference division ratio 2 4 8 16 32 64 128 256 Undefined 5 10 20 40 80 160 320
Phase detector current control, as shown in following table: ipump word C1 C0 00 01 10 11 Phase Detector charge current A 100 200 300 400
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5503 DCR Direct Conversion Receiver
test0, test1 Test point select as shown in following table: test1 0 0 1 1 test2 test0 0 1 0 1 tp1 disabled pump up M cnt prescaler tp2 disabled pump down N cnt modulus
Phase detector disable (1 = disable, 0 = enable)
(vco0, vco1) Vco select word as shown in following table: vco1 0 0 1 1 vco0 0 1 0 1 Low band VCO disabled enabled disabled undefined High band VCO disabled disabled enabled undefined
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5503 DCR Direct Conversion Receiver
ABSOLUTE MAXIMUM RATINGS Operation beyond maximum rating may permanently damage the device. PARAMETER Storage temperature Junction operating temperature Positive supply voltage (Vp) Voltage applied to any pin RATING -55 to 150 C +110 C -0.3 to 6V -0.3V to VCCn+0.3V
TARGET SPECIFICATIONS Unless otherwise specified: 0 < Ta < 70 C; positive power supply (VCCn) = +5.0 V 5%. OPERATING CHARACTERISTICS PARAMETER Supply current High level input voltage Low level input voltage High level input current Low level input current Input impedance, RFp Input signal range Input frequency range AGC Range DCR Gain, Lower Band Range DCR Gain, Upper Band Range Noise figure 2 order IIP 3 order IIP Lo Leakage VCO Characteristics Tuning range, Low OSC Tuning range, High OSC Phase Noise L1 = 8.2nH L2 = 27nH C1 = 1pF L1 = 3.9nH L2 = 22nH C1 = .6pF 10kHz offset 950 1100 -78 1150 1475 MHz MHz dBc/Hz
rd nd
CONDITION All outputs loaded
MIN
NOM 120
MAX 150
Vcc+0.3
UNIT mA V V uA uA
Digital I/O Characteristics (Din, Dclk) 2
Gnd - 0.3
0.8 100 - 400 50
Vin = Vcc - 1.0V Vin = 1.0V
RFn bypassed to ground with 100 pf
Receiver Characteristics Unless otherwise noted, input source impedance is 75 -58 950 0V < VAGC < 4V Fin = 950 MHz Fin = 1450 MHz Measured at maximum gain Vrf_in = -38 dBm/tone Vrf_in = -38 dBm/tone Measured at RFp -12 20 42 42 15 0 -10 -60 22 62 62 -38 1450 dBm MHz dB dB dB dB dBm dBm dBm
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5503 DCR Direct Conversion Receiver
OPERATING CHARACTERISTICS (continued) Low Pass Filter Interface IOLPF, QOLPF output imped. Filter Loss Filter Input Impedance Input impedance Voltage Gain Output impedance I/Q output amplitude -3dB frequency, Frf-Flo Buffer THD Amplitude and Phase Characteristics I/Q quadrature accuracy I/Q amplitude matching -3 -1 +3 +1 degree dB 1.0 75 1% 2% Freq = 30 MHz source match is by external R 50 1000 23 10 1.2 10 6db

I and Q Buffer Amplifier (each output loaded with 4pF in parallel with 20k) )
dB
Vpp MHz
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5503 DCR Direct Conversion Receiver
PACKAGE PIN DESIGNATIONS
(Top View)
48-TQFP 5503-CGT
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5503 DCR Direct Conversion Receiver
MECHANICAL DRAWING
8.7 (0.343) 9.3 (0.366)
8.7 (0.343) 9.3 (0.366)
INDEX 1
6.8 (0.267) 7.2 (0.283)
1.40 (0.055) 1.60 (0.063)
0.0 (0) 0.20 (0.008)
0.2 (0.008) Typ. 0.50 (0.0197) Typ.
0.60 (0.024) Typ.
48-Lead Thin Quad Flatpack
Note: Controlling dimensions are in mm
PART DESCRIPTION
5503 DCR Direct Conversion Receiver
ORDER NO.
5503-CGT
PACKAGE MARK
5503-CGT
Advanced Information: The Advanced Information data sheet is to be approved for Beta Site and advanced customer information purposes only. It is not intended to replace the electrical specification for the specific device it represents. This document will be updated and converted into a Final (Preliminary Data Sheet) upon completion of Design Engineering Validation. Design Engineering should review this documentation for its accuracy to the definition and the design goals for the product it represents. No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. Purchase of I C components of TDK Corporation or one of its sublicensed Associated Companies conveys a license under the Philips I C 2 2 Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, (714) 508-8800, FAX (714) 508-8877, http://www.tsc.tdk.com TDK Semiconductor Corporation 02/22/01- rev. G
2 2
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